Schottky barrier source/drain N-MOSFET using ytterbium silicide

ABSTRACT

An N-type Schottky barrier Source/Drain Transistor (N-SSDT) that uses ytterbium silicide (YbSi 2-x ) for the source and drain is described. The structure includes a suitable capping layer stack.

This is a divisional application of U.S. patent application Ser. No.11/126,031, filed on May 10, 2005, which is herein incorporated byreference in its entirety, and assigned to a common assignee; it claimspriority to U.S. Provisional Patent Application Ser. No. 60/570,126,filed on May 11, 2004, which is herein incorporated by reference in itsentirety.

FIELD OF THE INVENTION

The invention relates to nanoscale MOSFET architecture, in particular toan improved high performance N-type Schottky barrier source/drainMOSFET.

BACKGROUND OF THE INVENTION

SSDTs (Schottky barrier Source/Drain Transistors), where the highlydoped source/drain of the conventional MOSFET is totally replaced with asilicide, were first reported by M. P. Lepselter and S. Sze in 1968 (seeref. 1). Recently, SSDTs have received a great deal of attention due totheir excellent scaling properties and ease of fabrication and have beenproposed as an alternative to traditional MOSFETs for sub-100 nmintegration. See ref. 2 for example However, the drain current of a SSDTis suppressed by the Schottky barrier between source and channel,resulting in small drivability and low I_(on)/I_(off) ratio.

The drain current increases with decreasing barrier height. Thesimulation results of W. Saitoh et al (ref. 3) showed that the samedrivability as a conventional MOSFET can be achieved using low Schottkybarriers, i.e., for the channel length L_(C)<30 nm devices, about 0.25eV for P—SSDT and 0.1-0.15 eV for N—SSDT, respectively. In theliterature to date, PtSi is used for P—SSDT because the electron barrierheight of a PtSi/Si contact is about 0.86 eV while the correspondinghole barrier is 0.24 eV which almost meets requirements. Highperformance P—SSDT with PtSi has also been reported by the inventors(see ref. 4).

To date, N—SSDT has usually been based on erbium silicide because it isknown that ErSi_(2-x) has the lowest barrier height among the knownsilicides. This electron barrier height is about 0.28 eV (See ref. 6).However, the film morphology of ErSi_(2-x) formed by solid-statereaction of as-deposited Er and substrate Si, is quite poor due to itsisland-preferred growth mode (see ref. 7), resulting in larger thantheoretically expected leakage currents in the device.

The reported performance of N—SSDT is not as good as that of P—SSDT (seefor example, ref. 8). Moreover, the barrier height of the ErSi_(2-x)/Sicontact is very sensitive to the residual oxygen concentration in thechamber during Er deposition and annealing. Contacts prepared inconventional vacuum displayed larger barrier heights (0.37-0.39 eV)indicating that ultra high vacuum is necessary for ErSi_(2-x)fabrication, which makes the process inconvenient and costly.

Therefore, in order to improve the electrical performance of N—SSDT, itis very important to find a suitable way to reduce the barrier heightand to improve the silicide quality for N—SSDT. In this invention, asolution to this problem is disclosed which leads to lower electronbarrier height and better film morphology than that of ErSi₂ formed byan otherwise same process.

Following a routine search of the patent literature, the followingreferences of interest were found:

M. G. Jang et al, U.S. Pat. No. 6,693,294 B1, Feb. 17, 2004, “Schottkybarrier tunneling transistor using thin silicon layer on insulator andmethod for fabrication the same”, J. P. Snyder et al, U.S. Pat. No.6,495,882 B2, Dec. 17, 2002, “Short-channel Schottky barrier MOSFETdevice”, J. P. Snyder et al, U.S. Pat. No. 6,303,479 B1, Oct. 16, 2001,“Method of manufacturing a short channel FET with Schottky barriersource and drain contacts”, Omura, et al, U.S. Pat. No. 5,962,893, Oct.5, 1999, “Schottky tunneling device”, and J. D. Welch, U.S. Pat. No.5,663,584, Sep. 2, 1997, “Schottky barrier MOSFET systems andfabrication thereof”.

SUMMARY OF THE INVENTION

It has been an object of least one embodiment of the invention toimprove the electrical performance of N—SSDT devices by means of a moresuitable silicide than ErSi, the electron barrier height of anErSi_(2-x)/Si contact not being low enough for N—SSDT and the quality ofErSi_(2-x) being very sensitive to vacuum conditions.

Another object has been to provide a process for forming andmanufacturing said improved device.

These objects have been achieved by replacing erbium silicide withytterbium silicide. YbSi_(2-x) has lower barrier height than ErSi_(2-x),and its film quality is better than ErSi_(2-x) formed by the sameprocess.

The invention can be used to fabricate Schottky barrier source/drainMOSFETs, especially when the device size is scaled down to sub-50 nm.Replacing ErSi_(2-x) in N—SSDTs by YbSi_(2-x) improves its electricalperformance significantly with no accompanying disadvantages. It should,however, be noted that the present invention does not imply that othersilicides, such as ternary silicides and germano-silicide may not yieldsimilar improvements

Ytterbium silicide can be fabricated in a conventional vacuum system(base pressure about 2×10⁻⁷ torr), the morphology of the YbSi_(2-x) thatis formed from the silicidation solid-state reaction being much smootherthan that of ErSi_(2-x). To prevent oxidation of Yb and to improve thefilm quality, a suitable capping layer stack of Ti/HfN, was developed aspart of the invention. The annealing conditions for silicidation andselective etching procedures to remove unreacted Yb and the cappinglayer have also been optimized.

These YbSi_(2-x) based fabrication methods for SSDTs are fullycompatible with existing CMOS technologies as well as with newerindustry innovations including high-k dielectrics, metal gates, SOI, andstrained silicon. The self-aligned silicide S/D fabrication methodsinvolve the deposition of a Yb/Ti/HfN stack using e-beam evaporation orsputtering, silicidation using RTA (rapid thermal anneal) and/or furnaceanneal, and selective etching.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates the basic operation of a Schottky barrier MOSFETdevice.

FIG. 2 is a flow chart summary of the process of the present invention.

FIG. 3 is an X-ray spectrum confirming that the silicide formed isYbSi_(1.8).

FIGS. 4 a and 4 b illustrate the performance of the invented devicethrough plots of current density and capacitance as a function ofvoltage.

FIGS. 5 a and 5 b are plots of source-drain current as a function ofsource-drain voltage and source-gate voltage, respectively.

FIGS. 6-9 illustrate steps in the process of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In this invention a N—SSDT device having YbSi_(2-x) source and drain isdisclosed. The schematic structure and operating principles areillustrated in FIG. 1. Seen there are source 11, gate oxide 12, gateelectrode 13, and drain 14. In the off state, barrier 15 slopes awayfrom the P silicon-source interface and current flow is blocked. In theon state, the barrier is still present but has grown thin enough forcurrent to pass through it through Fowler-Nordheim tunneling.

To avoid the introduction of unnecessary detail, a simple single maskprocess, which has been demonstrated in our lab, is described here. Theperformance of the resulting device has been compared with that of anErSi_(2-x) S/D device fabricated by the same method. It will beunderstood that the basic principles of the invention will continue toapply to more detailed versions of this simplified process.

It is also important to note that the self-aligned YbSi_(2-x) processdescribed here is fully compatible with existing established CMOSfabrication processes, including SOI (silicon on insulator), strainedsilicon, metal gates, and high K dielectrics, in general withoutmodification.

FIG. 2 is a flow chart that summarizes the process of the invention. Yb,Ti and HfN are sequentially deposited, without breaking vacuum, using asputtering system. HfN is used as a capping layer to prevent Yboxidization during ex situ annealing. If vacuum annealing is used, thislayer is no longer necessary. A key feature of the invention is the Ticapping layer on the Yb layer; this has been found to improve theYbSi_(2-x) film quality slightly, probably because of a reduction of theoxygen concentration in the YbSi_(2-x) film. The capping layers andunreacted metal are removed by wet etching in HF solution (diluted1:100) for 3 minutes followed by H₂SO₄+H₂O₂ solution at 120° C. for 5minutes.

X ray diffraction results have shown that the silicide film that isformed is YbSi_(1.8) as evidenced by the data shown in FIG. 3. FIGS. 4 aand 4 b are the I-V and C-V curves, respectively of a YbSi_(2-x)/p-Sidiode. The hole barrier height and ideality factor deduced from the I-Vcurve are 0.82 eV and 1.04 respectively, the reverse bias leakagecurrent at 1V is about 1.1×10⁻⁶ A/cm², which is about 4 times smallerthan for ErSi_(2-x) (as reported by J. Larson et al. in ref. 5 where anMBE [molecular beam epitaxy] system was used). The barrier height anddoping level of the Si substrate deduced from the C-V curve are 0.88 eVand 5×10¹⁵ cm⁻³, respectively, which is close to the expected value.

FIGS. 5 a and 5 b are, respectively, the I_(ds)-V_(ds) and I_(ds)-V_(gs)curves of a N—SSDT having a source and drain of YbSi_(2-x). The EOT(effective oxide thickness) of the device is 2.5 nm. The subthresholdslope is ˜75 mV/dec and the I_(on)/I_(off) ratio is about 10⁷. TheI_(dsat) at V_(ds)=V_(gs)=1.5V is about 7.5 μA/μm for the L_(g)=4 μmdevice, close to that of P-SSDT with PtSi. The performance of the deviceis much better than the device fabricated using the same method but withErSi₂ S/D, and it is better than other reported data of N-SSDT in theliterature so far. Thus, these results show that YbSi_(1.8) is asuperior material to be integrated in N-SSDTs than the ErSi_(1.7) thatthe prior art has employed to date.

Now follows a more detailed account of the process of the presentinvention:

Referring now to FIG. 6, the process begins with the provision of aP-type silicon wafer 10 and depositing thereon layer of hafnium oxide 62(to a thickness of between about 3 and 10 nm) which is then heated atbetween about 500 and 700° C. for between about 10 and 60 minutes. Nextcomes the deposition of layer 63 of hafnium nitride (to a thickness ofbetween about 20 and 200 nm) on the layer of hafnium oxide followingwhich layer 64 of tantalum nitride is deposited on this layer (to athickness of between about 20 and 200 nm).

A suitable etch mask is then used to form the gate structure, by etchingall unprotected surfaces until the silicon surface is exposed. After theetch mask has been fully removed the wafer is immersed in dilute (100:1)HF. The resulting structure is shown in FIG. 6. Sidewall spacers wouldnormally be added to protect the gate pedestal from diffusion but arenot shown here for purposes of simplification.

Next, in a key feature of the invention, layer 71 of ytterbium is laiddown (to a thickness of between about 5 and 50 nm) followed by cappinglayer of titanium 72 (to a thickness of between about 1 and 10 nm) andthen by second layer of hafnium nitride 73 (to a thickness of betweenabout 50 and 200 nm), as shown in FIG. 7. The deposition of these threelayers takes place during a single pump down for which the pressure ismaintained at all times at a pressure below about 5×10⁻⁷ torr.

After suitable patterning (not shown but, for example, a liftoff resist)that defines opposing source and drain regions immediately adjacent tothe gate, as shown in FIG. 7, the structure is heated in a rapid thermalannealing system or a furnace in forming gas at a temperature betweenabout 400 and 600° C. for about 1 hour to perform the solid-statereaction of Yb and substrate Si, resulting in the formation of ytterbiumsilicide source and drain regions 81 and 84 respectively (see FIG. 8).

The process concludes with selective etching in dilute HF at roomtemperature for about 3 minutes and then in a mixture of sulphuric acidand hydrogen peroxide at about 120° C. for about 5 minutes sequentially.This results in the removal of the titanium and hafnium nitride layersas well as of any unreacted ytterbium. The ytterbium silicide in sourceand drain remain. The completed structure then has the appearanceschematically illustrated in FIG. 9.

REFERENCES

-   [1] M. P. Lepselter and S. Sze, “SB-IGFET: An Insulated gate    field-effect transistor using Schottky barrier contacts as source    and drain”, Proc. IEEE, 56, 1968-   [2] L. E. Calvet, H. Luebben et al, “Subthreshold and scaling of    PtSi Schottky barrier MOSFETs”, Supperlattices and Microstructures,    Vol. 28, No. 5/6, 2000, pp. 501-506-   [3] W. Saitoh, A. Itoh, S. Yamagami and M. Asada, “Analysis of    Short-Channel Schottky Source/Drain Metal-Oxide-Semiconductor    Field-Effect Transistor on Silicon-on-Insulator Substrate and    Demonstration of Sub-50-nm n-type Devices with Metal Gate”, Jan J.    Appl. Phys. 38, 1999, pp. 6226-6231-   [4] Shiyang Zhu et al., “Low temperature MOSFET technology with    Schottky barrier source/drain, high-k gate dielectric and metal gate    electrode”, presented in ISDRS 2003, submitted to Solid State    Electronics-   [5] J. Larson, J. Snyder, “Schottky Barrier CMOS: Technology    Overview, 2003-   [6] P. Muret, et al, “Unpinning of the Fermi level at erbium    silicide/silicon interfaces”, Physical Review B, Vol. 56, No. 15,    1997, pp. 9286-9289-   [7] C. H. Luo, et al, “Growth kinetic of amorphous interlayers and    formation of crystalline silicide phases in ultrahigh vacuum    deposited polycrystalline Er and Tb thin film on (001) Si”, J. Appl.    Phys. 82(8), 1997, pp. 3808-3814-   [8] J. Kedzieski, et al, “Complementary silicide source/drain    thin-body MOSFETs for the 20 nm gate length regime”, IEDM, 2000, pp.    57-60-   [9] M. Jang et al, “Characteristics of erbium-silicided n-type    Schottky barrier tunnel transistors”, Appl. Phys. Lett., 83(13),    2003, pp. 2611-2613

1. A Schottky barrier source/drain MOSFET structure, comprising: on alayer of P-type silicon, a gate structure having a gate electrode on alayer of gate insulation; and source and drain regions, that compriseytterbium silicide, on opposing sides of said gate electrode.
 2. Thestructure described in claim 1 wherein said layer of gate insulation ishafnium oxide.
 3. The structure described in claim 2 wherein said layerof gate insulation is between about 3 and 10 nm thick.
 4. The structuredescribed in claim 1 wherein said gate electrode is hafnium nitride. 5.The structure described in claim 4 wherein said gate electrode isbetween about 20 and 400 nm thick.
 6. The structure described in claim 1wherein said layer of P-type silicon has a resistivity between about 0.1and 50 ohm-cm.